1. Field of Invention
The present invention relates to semiconductor, and more particularly to a semiconductor wafer and its manufacturing process thereof, wherein the terminal pad is disposed along a scribe line of a semiconductor wafer to enlarge the usage area of the analog IC die.
2. Description of Related Arts
A conventional semiconductor wafer comprises a wafer body and a plurality of dies spacedly formed on the wafer body to define a scribe line as a margin between each two dies. Accordingly, each of the dies, which is also called as an analog IC chip, is an integrated circuit consisting of silicon based substrate.
Before each of the dies is cut into an individual component, a wafer test must be performed to ensure each of the dies is functioning in an optimum condition. Generally, each of the dies comprises a plurality of bond pads and a plurality of terminal pads spacedly formed within the die, wherein the terminal pads can be test pads for measuring the voltage of the die via a measuring tool, such as probe card, or trim pads for trimming the reference voltage of the die and the reference function thereof.
Accordingly, there are two trimming methods, which are laser cut and electrical test, are commonly used for trimming the dies. The laser cut is performed to trim the trim fuse such that the properties of dies are corresponding changed once the trim fuse is cut. However, the operation of the laser cut is costly and complicated so as to highly increase the manufacturing cost of the die. In addition, during the operation of the laser cut, the voltage of each of the dies cannot be predicted so that the quality of each of the dies cannot be standardized.
Another trimming method is preformed by electrical trim, wherein an electric current is applied on each of the dies to trim the trim fuse. Since the electrical current can be selectively controlled, the trim fuses can be selectively removed from the dies so as to generate the reference voltage of the die and the reference function thereof.
Furthermore, the conventional semiconductor wafer has several drawbacks. Since the terminal pads are disposed within each of the dies, the size of the die must be big enough to hold the bond pads, the terminal pads, and the trim fuses in position. Therefore, the limited size of each of the dies can only hold up to a certain number of pads thereon. In other words, the complicated integrated circuits are limited on the size of each of the dies so as to highly increase the manufacturing cost of the semiconductor wafer.
In addition, when the dies are cut off from the semiconductor wafer, the terminal pads are stayed on each of the dies. It is worth to mention that the terminal pads are only used for measuring the voltage of the corresponding die or programming the trim fuse. The terminal pads are useless after the measurement. Therefore, the terminal pads will used up the limited space of each of the dies.